Standards Support

UVM

SystemRDL

IP-XACT

Using the word “standards” is often misleading with respect to specifying the hardware/software interface, and there remains considerable misunderstanding around the original purpose of the existing formats and what they can realistically be expected to deliver.

Many standards in use today were initiated by one or more vendors promoting a proprietary format of convenience – some were spun out as commercial offerings, some presented as core technologies to the consortia of the day or both.

Semifore has been involved with industry standards since their inception. We have watched the intrigue that surrounds and limits their development. We have realized that technology and market demands are traveling much faster than standards can evolve. We have realized that in truth, the current standards portfolio is not helping the teams whose job it is to bring products to market efficiently.

Semifore was formed specifically to accomplish this task by providing tools and a methodology that will always be a superset of all prevailing standards across design, verification, software, and documentation teams. These tools compile at a speed that allows multiple revisions in minutes, not days. No matter how many design revisions, with the CSRCompiler™ system all teams benefit from a single-source specification that auto-generates all necessary views. And instantly regenerates them for each revision. We minimize risk to projects, profit, customers and careers.

Unique among peer companies, Semifore participates in the Accellera IP-XACT, UVM, Portable Stimulus and SystemRDL (now dormant) working groups. This is a testament to both our industry recognition and depth of the standards understanding we bring to our customers.

Support for UVM

UVM

  • Semifore is an active member of the IEEE 1800.2 Working Group and Accellera Portable Stimulus Working Group
  • CSRCompiler automatically generates the register class instances based on the UVM RAL
    • Backdoor paths
    • Randomization and constraints
    • Coverage
    • Verilog and VHDL header files
    • Register class i