Josh Rensch, Author at Semifore

About Josh Rensch

Josh Rensch joined Semifore in 2019 to help customers succeed with their projects. He worked for big and small companies, leading verification teams in both FPGA and ASIC worlds, in both defense industries and commercial. Throughout it all, he's dealt with verifying and ensuring documentation of registers and address maps. He brings that knowledge to Semifore and its customers.

Tips for Architecting the Hardware/Software Interface

Over the years, working with customers designing chips, a few guidelines have been found that assist in the architecture of the Hardware/Software Interface (HSI). Sometimes guidelines will be broken. Sometimes for legacy designs, sometimes because not all the requirements are upfront but keeping these in mind help ensure the architecture will be as robust and […]

By Josh Rensch|2022-09-20T13:49:17-07:00September 19th, 2022|

Why IP-XACT Should Not Be Used to Define Registers

In search of determining a language used to define the HSI (Hardware/Software Interface), inevitably IP-XACT is brought up. Engineering teams consider it because it is an IEEE standard. It contains information on registers and address maps and may be a deliverable for their product. Also, IP vendors supply IP-XACT descriptions of their […]

By Josh Rensch|2022-08-19T13:00:59-07:00August 11th, 2022|