Standards Support




Using the word “standards” is often misleading with respect to specifying the hardware/software interface, and there remains considerable misunderstanding around the original purpose of the existing formats and what they can realistically be expected to deliver.

Many standards in use today were initiated by one or more vendors promoting a proprietary format of convenience – some were spun out as commercial offerings, some presented as core technologies to the consortia of the day or both.

Semifore has been involved with industry standards since their inception. We have watched the intrigue that surrounds and limits their development. We have realized that technology and market demands are traveling much faster than standards can evolve. We have realized that in truth, the current standards portfolio is not helping the teams whose job it is to bring products to market efficiently.

Semifore was formed specifically to accomplish this task by providing tools and a methodology that will always be a superset of all prevailing standards across design, verification, software, and documentation teams. These tools compile at a speed that allows multiple revisions in minutes, not days. No matter how many design revisions, with the CSRCompiler™ system all teams benefit from a single-source specification that auto-generates all necessary views. And instantly regenerates them for each revision. We minimize risk to projects, profit, customers and careers.

Unique among peer companies, Semifore participates in the Accellera IP-XACT, UVM, Portable Stimulus and SystemRDL (now dormant) working groups. This is a testament to both our industry recognition and depth of the standards understanding we bring to our customers.

Support for UVM


  • Semifore is an active member of the IEEE 1800.2 Working Group and Accellera Portable Stimulus Working Group
  • CSRCompiler automatically generates the register class instances based on the UVM RAL
    • Backdoor paths
    • Randomization and constraints
    • Coverage
    • Verilog and VHDL header files
    • Register class instances based on the proposed Accellera UVM-SystemC register abstraction layer
  • CSRCompiler saves the verification team valuable time that can be spent on the task of verifying the device under test
    • Eliminates the error-prone process of entering information manually
    • Keeps the verification team in sync with the design as it evolves

Support for SystemRDL


  • CSRCompiler is the only commercially available tool that can read and write SystemRDL-based designs and data
  • With SystemRDL 1.0, the user community added user-defined properties (UDPs) through significant PERL scripting to overcome the gaps in SystemRDL and Blueprint (originally from Denali)
  • SystemRDL is a useful alternative to Blueprint, which is no longer available after Cadence’s acquisition of Denali
  • CSRCompiler reads Blueprint SystemRDL and SystemRDL 1.0
  • CSRCompiler creates SystemRDL 1.0 and SystemRDL 2.0

Support for IP-XACT


  • Semifore is one of the authors of the IP-XACT standard
  • IP-XACT is an Accellera standard for packaging, integrating, and reusing IP
  • IP-XACT is often implemented as a GUI front-end for design and verification teams to generate small designs or integrate IP
  • Companies perform full-chip assembly based on IP-XACT
  • Companies perform IP block connectivity based on IP-XACT
  • IP-XACT supports third-party IP exchange / documentation formats from ARM, Synopsys, Cadence and other suppliers

IP-XACT Limitations for Register RTL Generation

  • IP-XACT is a file format that specifies how blocks of RTL are interconnected. Its focus is on the block ports
  • Large, advanced designs cannot use GUI-type solutions like IP-XACT to complete RTL implementation
  • IP-XACT requires setup scripts to implement RTL generation of registers
  • Large complex designs require features like templates, wide register support, back door paths, etc. that are not in the IP-XACT standard
  • IP IP-XACT contains netlist and port addresses, but no behavioral / design intent data

Semifore: An enhanced methodology for IP-XACT

  • Users can create synthesizable RTL for control registers
  • Users can create chip software interface headers and perform class instances
  • CSRCompiler:
    • Natively specifies control register behavior
    • Reads and writes all versions of IP-XACT for model checking and generation
    • Does not need scripts to implement RTL
    • Validates IP-XACT models with over 1,000 syntax and semantic checks
    • Automates software register RTL with support for >1M firmware registers
    • Generates customized C-header files, class instances and back door paths
    • Documents activity continuously across user teams (software, RTL, verification, tech pubs)
    • Supports templates and wide registers

Portable Stimulus

Portable Stimulu logoSemifore has been an active member of the Accellera Portable Stimulus Working Group since its inception, contributing our expertise to formulate a model for representing the HSI in the Portable Stimulus standard.