Using the word “standards” in this emerging market is often misleading, and there remains considerable misunderstanding around the original purpose of these formats and what they can realistically be expected to deliver.
Many “standards” in use today were initiated by one or more vendors promoting a proprietary format of convenience – some were spun out as commercial offerings, some presented as core technologies to the consortia of the day, some both.
Semifore has been involved with industry standards since their inception. We have watched the intrigue that surrounds and limits their development. We have realized that technology and market demands are traveling much faster than standards can evolve, and we have realized that in truth, the current standards portfolio is not helping the teams whose job it is to bring chips to market efficiently.
Semifore was formed specifically to do that by providing functionality that will always be a superset of all prevailing standards across design, verification, software, and documentation teams, and compile at a speed that allows multiple revisions in minutes, not days. No matter how many design revisions, with CSRCompiler all teams benefit from a single-source specification that auto-generates all their necessary views. And instantly regenerates them for each revision. We minimize risk to projects, profit, customers and careers.
Unique among peer companies, Semifore participates in the Accellera IP-XACT, UVM and SystemRDL working groups, which is a testament to both our industry recognition and depth of the “standards” understanding we bring to our customers.
- Semifore is one of the authors of the SystemRDL 1.0 standard and the reference tool for Validating SystemRDL 1.0
- There are many missing features and concepts in SystemRDL
- The user community added UDPs by significant PERL scripting to overcome the gaps in SystemRDL and Blueprint
- SystemRDL 2.0 is currently being developed by a working group of Accellera which Semifore is a significant contributor
- Post Denali acquisition Blueprint is no longer available from Cadence and customers are looking for an alternative
- CSRCompiler is the only commercially available tool that can read and write SystemRDL based designs, data, and encompasses the most current features required to get your RTL generated using this format
- CSRCompiler is backwards compatible to SystemRDL 1.0 and will fully support SystemRDL 2.0 when completed and published
Support for UVM
- Semifore is an active member of the IEEE 1800.2 Working Group and Accellera Portable Stimulus Working Group
- CSRCompiler automatically generates the register class instances based on the UVM RAL
- Backdoor paths
- Randomization and constraints
- Verilog and VHDL header files
- Register class instances based on the proposed Accellera UVM-SystemC register abstraction layer
- CSRCompiler saves the verification team valuable time that can be spent on the task of verifying the DUT
- Eliminates the error-prone process of entering information manually
- Keeps the verification team in sync with the design as it evolves
Support for IP-XACT
- Semifore is one of the authors of the IP-XACT standard
- IP-XACT is an Accellera standard for packaging, integrating, and reusing IP
- IP-XACT is often implemented as a GUI front-end for designers and verification teams to generate small designs or integrating IP
- Companies perform Full Chip assembly based on IP-XACT
- Companies perform IP block connectivity based on IP-XACT
- IP-XACT supports third party IP exchange / documentation format from ARM, Synopsys, Cadence and other suppliers
IP-XACT Limitations for Register RTL Generation
- IP-XACT is a file format that specifies how blocks of RTL are interconnected. Its focus is on the block ports.
- Large advanced chips cannot use GUI-type solutions like IP-XACT to complete RTL implementation
- IP-XACT requires setup scripts to implement RTL generation of registers
- Large complex designs require features like templates, wide register support, back door paths, etc. which are not in the IP-XACT Standard
- IP IP-XACT contains netlist and port addresses, but no behavioral / design intent data
Semifore: Kicking IP-XACT up a notch (or 10)
- Users can create synthesizable RTL for control registers
- Users can create chip software interface headers and perform class instances
- The CSRCompiler and IP
- Natively specifies control register behavior
- Reads and writes all versions of IP-XACT for model checking and generation
- Does not need scripts to implement RTL
- Lints IP-XACT models with over 1,100 syntax and semantic checks
- Automates SW Register RTL with support for >1M firmware registers
- Generates customized C-Header files, class instances and back door paths
- Documents activity continuously across user teams (software, RTL, verification, tech pubs)
- Supports templates, wide registers